Semiconductor fabrications have long utilized electrical interconnects with solder microbonding. Simplistically, a copper bump may be formed on a wafer, a sacrificial layer is applied on top of the copper bump and a cavity formed, solder is reflowed into the cavity, and the layer is stripped off of the wafer. The result of the process is a solder bump which may be replicated on various locations on the wafer. However, current methodologies may produce inconsistencies in the resultant solder bumps. Improved solder bump configurations are desired.